module _12bitBIN2BCDb (Bin,BCD2,BCD1,BCD0);
input [11:0] Bin;
output reg[3:0] BCD2,BCD1,BCD0;
reg [25:0] z;
integer k;
always @(Bin)
begin
for(k=0;k<=25;k=k+1)
  z[k]=0;
  z[14:3]= Bin;
repeat(9)
begin
if(z[15:12]>4)
z[15:12]=z[15:12]+3;
if(z[19:16]>4)
z[19:16]=z[19:16]+3;
if(z[22:20]>4)
z[23:20]=z[23:20]+3;
z[25:1]=z[24:0];

end
{BCD2,BCD1,BCD0}=z[25:12];
end
endmodule
